Senior SystemVerilog RTL Design Engineer - IP/PHY
Intel
Intel's HIPD team seeks a senior Logic design engineer for UCIE PHY IP in datacenter/server designs. You will develop RTL, define architecture features, and ensure design quality from RTL to timing convergence. The role requires strong SystemVerilog expertise, collaboration across geographies, and a fast ramp on complex IPs in a dynamic environment. Hybrid work model offered in the US. #J-18808-Ljbffr Intel
Vacancy posted 1 day ago
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