Senior ASIC Design Lead: RTL to Tapeout
$250k - $280kEridu AI
Eridu AI, a Silicon Valley–based hardware startup, seeks a hands‑on ASIC Chip Design Lead to own RTL, micro‑architecture, and full‑chip integration from spec to signoff in a fast‑paced environment in Saratoga, CA. You will drive RTL development in Verilog/SystemVerilog, collaborate with Physical Design on timing closure, and guide tape‑out efforts. Base salary range 250,000–280,000 USD per year; market practices apply. #J-18808-Ljbffr Eridu AI
Vacancy posted 2 days ago
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