Physical Design Engineer

Job Details:

Job Description:

About Altera

At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

Altera is seeking a motivated Physical Design Engineer to join our Physical Design organization. In this role, you will support the implementation of custom IP and SoC designs from RTL through GDS, gaining hands-on experience across key stages of the physical design flow.

You will work alongside experienced physical design engineers and collaborate with RTL, timing, DFT, verification, and CAD teams to support implementation, analysis, optimization, and signoff activities for next-generation FPGA products. This role provides an opportunity to develop expertise in physical design methodologies, industry-standard EDA tools, and semiconductor design flows while contributing to real product development.

Responsibilities

• Perform physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.

• Support aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.

• Support verification and signoff activities including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.

• Analyze physical design and verification results and work with experienced engineers to identify and resolve design violations.

• Develop knowledge of various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.

• Support design optimization activities to improve product-level parameters such as power, frequency, and area.

• Work with senior engineers to troubleshoot physical design, timing, placement, routing, and verification issues.

• Participate in the development and improvement of physical design methodologies and flow automation.

• Support the execution, documentation, and improvement of physical design flows and methodologies.

• Collaborate with cross-functional engineering teams to support successful implementation and delivery of designs.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$100,000 - $110,000 USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

#LI-MD1

Qualifications:

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.

• 1+ year of experience in Physical Design engineering or Physical Design flows.

Preferred Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

• Experience with RTL-to-GDS physical design flows.

• Experience with one or more physical design activities, including synthesis, floorplanning, placement, routing, clock tree synthesis, or static timing analysis.

• Experience with industry-standard EDA tools such as Synopsys, Cadence, Siemens EDA, or equivalent.

• Experience with static timing analysis or timing closure.

• Exposure to physical verification activities, including DRC, LVS, ERC, or related checks.

• Exposure to power analysis, IR drop, electromigration, signal integrity, or power integrity.

• Exposure to DFT, scan implementation, or related design-for-test methodologies.

• Experience with scripting languages such as Python, Tcl, Perl, or Shell.

• Academic, internship, or co-op experience involving semiconductor physical design, ASIC/SoC implementation, VLSI, or related design flows.

• Knowledge of digital logic design, CMOS technology, semiconductor design methodologies, and VLSI fundamentals.

• Strong analytical and problem-solving skills with an interest in physical implementation and semiconductor design.

• Ability to work effectively with senior engineers and cross-functional engineering teams.

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

San Jose, California, United States

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.