Senior Verification Engineer: UVM/SystemVerilog Expert
$163k - $237kGoogle Inc.
Google Inc. is seeking an experienced verification engineer based in Mountain View, California. The role requires expertise in verification methodologies and developing test environments while collaborating with design engineers to ensure robust testing of digital design blocks. The ideal candidate holds a Bachelor's degree in a relevant field, possesses 8 years of experience in verification, and is proficient in SystemVerilog and UVM. The position offers a competitive salary ranging from $163,000 to $237,000, plus bonuses and equity. #J-18808-Ljbffr Google Inc.
- Software Technology, Inc. is looking for a skilled FPGA Verification Engineer to join our team in Santa Clara, CA. The successful candidate... ...a strong background in FPGA design, experience with UVM and SystemVerilog, and excellent problem-solving skills. This is an onsite...SeniorWork at office
- ...A leading engineering company is seeking a highly skilled FPGA Verification Engineer in Santa Clara, CA. You will verify complex FPGA designs, collaborating... ...experience in FPGA and strong proficiency in UVM and SystemVerilog. This is a full-time onsite role, requiring a...SuggestedFull time
- ...An established industry player is seeking a skilled verification engineer with extensive experience in UVM and SystemVerilog. This role involves defining and implementing a comprehensive verification environment, writing test plans, and debugging RTL and gate-level netlists...Senior
- A leading technology firm seeks a skilled FPGA Verification Engineer in Mountain View. This role involves verifying FPGA designs with advanced methodologies and requires strong expertise in SystemVerilog, UVM, and debugging skills. The ideal candidate will develop verification...Suggested
- A leading technology company is seeking a Senior Verification Engineer to join their multi-media IP team. The ideal candidate will have at least 5 years of design verification experience, particularly in verifying sophisticated IPs using System Verilog. Responsibilities...Senior
- A leading technology company in Santa Clara is looking for a Design Verification Engineer to ensure the functionality and performance of their SOCs. The role involves developing test plans, collaborating with design teams, and verifying various hardware components. The...Senior
$75 - $80 per hour
...leading aerospace company is seeking an Electrical Design and Analyst Engineer to work in Mountain View, CA. This contract role focuses on ASIC/FPGA verification, requiring expertise in SystemVerilog and a Bachelor's degree in a relevant field. You will be responsible for...Hourly payContract work- ...looking for an experienced Hardware Verification & Validation Engineer in Sunnyvale, California. This role... ...silicon validation, and developing robust UVM testbenches for PCIe interfaces. The... ...coding skills in Python, C/C++, and SystemVerilog. Comprehensive benefits and...Senior
- ...Expertise in ASIC/SoC verification using HVLs. Knowledge of networking protocols will be an addedadvantage. Expertise in SystemVerilog, System C,Verification Methodologies such as OVM,UVM,etc. Should have worked on at least one full-chip or module-level verification using...Senior
$126.8k - $220.9k
A leading technology company in Sunnyvale, California seeks a Wireless PHY Design Verification Engineer to develop and implement advanced verification strategies for WiFi SoCs. The role demands sophisticated test environments and strong experience in wireless and DSP systems...$150k - $165k
...Encore Semi Llc in Sunnyvale, CA is seeking a Sr Design Verification Engineer to oversee digital system verification, focusing on ARM-... ...of ASIC verification experience, and strong expertise in SystemVerilog and UVM. This full-time role offers a competitive base salary...SeniorFull time$120k - $225k
...Description We’re hiring experienced Design Verification Engineers to play a key role in developing and... ...development and execution using UVM or other advanced DV methodologies.... ...subsystems. ~ Understanding of Verilog, SystemVerilog, and UVM. ~ Proven track record of first...Senior$85 - $107 per hour
...Downtown Boulder Partnership is seeking a Senior Design Verification Engineer to lead verification teams in Santa Clara, CA. This role involves defining verification plans, creating UVM/SystemVerilog testbenches, and ensuringdesign quality. The ideal candidate will possess...Senior$170k - $235k
...A leading aerospace company is seeking a Sr. ASIC Design Verification Engineer for its Starshield team in Palo Alto, California. The role... ...engineering, 5+ years in design verification, and experience with SystemVerilog. Competitive salary between $170,000 and $235,000 per year...Senior$156k - $229k
...Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science... ...8 years of experience with design verification. Experience with SystemVerilog. Preferred qualifications:... ...exceptional verification. Using your UVM and SystemVerilog coding and problem...SeniorFull timeWorldwide- ...We are looking for a Senior Verification Infrastructure Engineer to join the SoC verification team at NVIDIA. In this role, you will build, develop... ...experience 8+ years in the following areas: SystemVerilog, UVM, and modern verification methodologies Experience working...Senior
- ...NVIDIA, we are redefining the future of computing! As a Senior Verification Engineer on our CPU Verification Team, you will play a pivotal... ...constrained‑random verification environment using SystemVerilog and UVM. Proficient in one or more scripting languages like Python...SeniorWork experience placement
$138k - $198k
...digital design blocks in Mountain View, CA. This role demands a Bachelor's degree in Electrical Engineering or Computer Science along with practical experience using SystemVerilog and other relevant tools. The compensation for successful candidates ranges from $138,000 to...- Apply advanced verification methodologies to verify memory subsystem... ...functional test plans; build UVM‑based constrained random test... ...’s degree in Electrical Engineering and four years of experience... ...: Python scripting, Verilog/SystemVerilog/UVM; RTL simulation tools (Synopsys...Senior
$116k - $189.75k
NVIDIA Corporation in Santa Clara is seeking an ASIC Clocks Verification Engineer to collaborate with ASIC designers and verification... ...in Electrical Engineering and practical experience with SystemVerilog, UVM, and strong scripting skills in Python or Perl. The position...Senior- NVIDIA Corporation is hiring a Senior ASIC Verification Engineer in Santa Clara, California. This position involves verifying designs and implementations... ...+ years of relevant experience, and be proficient in SystemVerilog and UVM. The role provides a competitive salary range of $136...Senior
- ...coherency fabric (SCF). Use advanced verification methods, including sophisticated verification... ...verification infrastructure using SystemVerilog and UVM. Collaborate with architects,... ...team. Track record of mentoring junior engineers and interns (plus). Strong background...SeniorNight shift
- NVIDIA is hiring a Senior Verification Engineer for its Emulation division, located onsite in Santa Clara... ..., SpeedBridges, and Accelerated UVM Testbenches. Bring up SOCs on emulation... ...Proficiency in Verilog and/or VHDL, C/C++, and SystemVerilog. Experience with UVM verification...SeniorWork at office
$136k - $218.5k
Senior ASIC Verification Engineer page is loaded## Senior ASIC Verification Engineerlocations: US, CA, Santa Claratime type: Full timeposted on... ...Oriented Programming principles and proficient in SystemVerilog/UVM.* Familiarity with memory subsystem concepts such as memory...Senior$168k - $264.5k
NVIDIA is looking for a Verification Engineer to join our Emulation division. We are a worldwide recognized... ...Estimation, SpeedBridges, Accelerated UVM Testbenches). Bring up SOCs on... ...in Verilog and/or VHDL, C/C++ and SystemVerilog. Experience with UVM verification environments...SeniorWorldwideFlexible hours$136k - $218.5k
...As a Senior Digital Design Verification Engineer at NVIDIA, you'll verify the design and implementation of our... ...verification methodologies such as UVM. Build reusable bus functional models... ...system/SOC level and expertise in SystemVerilog a must. Experience using random...Senior- ...Title: Lead / Senior Verification engineer Location: San Jose, CA... ...Rate: $Open Skills: UVM and System Verilog... ...• Strong experience in SystemVerilog and UVM verification methodologies... ...Ajith Kumar |Sourcing Expert TWO95 International Inc,...Senior
$200k
...a team of exceptional architects and engineers to rethink how AI, sensing, memory, and... ...Role We are looking for talented Design Verification Engineers to help verify and deliver... ...Build verification environments using SystemVerilog, UVM, C/C++, assertions, formal verification...SeniorFlexible hours$170k - $235k
...of enabling human life on Mars. SR. ASIC DESIGN VERIFICATION ENGINEER (STARSHIELD) Starshield leverages SpaceX’s Starlink... ...test harnesses and test sequences Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks...SeniorTemporary workWeekend work- ...Devices is looking for a skilled Design Verification Engineer to join the Network Technologies... ...Group. This role involves developing UVM-based testbench architectures and leading... ...ideal candidate should have expertise in SystemVerilog, strong debugging skills, and the...Senior
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