DFT Engineer
$140k - $210kNutanix
Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.The Digital ASIC Design Team is currently seeking candidates who will be responsible for the implementation and verification of advanced DFT /DFD (Design for Test/Design for Debug) techniques for low power, multi voltage designs.The successful candidate will help in the deployment of DFT methodologies that reduce test cost, increase product quality, and enhance yield learning on leading edge process technologies. The candidate should have solid hands-on experience with industry standard DFT techniques such as scan and MBIST.Job responsibilities include DFT pattern generation, coverage analysis and debug as well as running and debugging gate level simulations. The ideal candidate will have experience in both pre, and post-silicon in the DFT domain.All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.Preferred Qualifications10+ years industry experience in the implementation and verification of advanced DFT /DFD (Design for Test/Design for Debug) techniques for low power and multi voltage domain designs. A strong fundamental knowledge of DFT is requiredUnderstanding of core-based test methodology and scan isolation.Knowledge of various fault models such as Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and Cell Aware.Knowledge in JTAG, Scan Compression, ATPG, Fault Simulation and at-speed testing.Experience with industry EDA ATPG and insertion tools.Experience in DFT implementation, Scan/ATPG, MBIST insertion/validation, coverage analysis.Minimum Qualifications:Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.ORMaster's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.ORPhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail View email address on click.appcast.io or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.Pay range and Other Compensation & Benefits :$140,000.00 - $210,000.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link .If you would like more information about this role, please contact Qualcomm Careers . #J-18808-Ljbffr
- ...company based in California seeks a motivated Lead Test Development Engineer to implement innovative manufacturing test solutions. The role... ...least 10 years of relevant experience and strong proficiency in DFT architecture and silicon validation. This position offers...Suggested
- ...Job Description Position: Sr DFT Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Design and implement DFT, including scan, MBIST, ATPG, Sims, Post-Si diagnosis at block and SoC level Verify test patterns using gate-level simulations. Collaborate...SuggestedFull timeTemporary workWork at officeRemote work
- ...Job Details Job Type (Permanent/Contract) : Permanent Pay Range: Job Title: DFT engineer Location: Santa Clara CA Tax Term (W2, C2C): Fulltime Job Type (Permanent/Contract) : Permanent Duration: Fulltime Pay Range: Description Familiarity with the Siemens suite of DFT...SuggestedPermanent employmentFull timeContract work
- Intelliswift - An LTTS Company is looking for a skilled professional to handle responsibilities related to DFT tools. You will work with the Siemens suite for DFT insertion, MBIST Repair Implementation, and verification of features like Boundary Scan and JTAG. The role...Suggested
$136k - $218.5k
Responsibilities Drive timing analysis and closure for DFT logic on all Nvidia chips (GPUs/CPUs/DPUs/LPUs/SoCs) at all hierarchical... ...BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with...Suggested- ...Role Purpose We are hiring a DFT Engineer with hands-on experience in Scan, ATPG, MBIST, or Boundary Scan. Job Details Job title: DFT Engineer Location: Santa Clara, CA Duration: Long term Experience: 8-15 Years Key Responsibilities Work on Scan insertion, ATPG, GLS (...
- ...Our client is looking for a Fulltime DFT Engineer for a project in Santa Clara, CA (Onsite). Below are the details. Job Title: DFT Engineer Required Skills & Qualifications 5+ years of hands‑on experience in DFT and ATPG for SoC or ASIC design Strong understanding of...Full time
- ...Santa Clara for a role focusing on timing analysis and closure for DFT logic across its chips, including GPUs, CPUs, and SoCs. The... ...and a minimum of 5 years of experience in Electrical or Computer Engineering. You will collaborate across teams to drive timing constraints...
$135k - $160k
...is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world...Permanent employmentTemporary workWorldwideWeekend work$142.2k - $213.4k
A leading tech company is seeking a DFT Engineer to work closely with chip architects and designers on mixed signal and digital VLSI designs. The role involves creating test vectors, validating DFT requirements, and ensuring high test coverage. Ideal candidates will have...- SpaceX is seeking a Sr. ASIC DFT Engineer to develop advanced ASICs for space and ground infrastructures. This role involves optimizing DFT architectures and collaborating with various engineering teams to enhance the Starlink network's capabilities. Ideal candidates will...
- United States Digital Space LLC in Sunnyvale is looking for a Sr. ASIC DFT Engineer. You will develop next-generation ASICs to enable connectivity in innovative space applications. Collaborating with cross-functional teams, the role includes optimizing DFT architectures...
- SpaceX is seeking a motivated Sr. ASIC DFT Engineer for their team in Sunnyvale, California. The engineer will work on developing next-generation ASICs for deployment in space and ground infrastructures. Responsibilities include optimizing DFT architectures and collaborating...
$100k - $180k
...Job Title: DFT Engineer City: Santa Clara State/Province: California Posting Start Date: 5/20/26 Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative...Minimum wageLocal area- NetApp, Inc. is seeking a PCBA Test Engineer in Santa Clara, California, responsible for end-to-end manufacturing test readiness for complex hardware platforms. This role involves leading execution of ICT and Boundary Scan tests, collaborating with hardware design teams...Contract work
$142.2k - $213.4k
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for...Work experience placementWork from home$116k - $166k
Minimum Qualifications Bachelor's degree in Electrical Engineering, a related technical field, or equivalent practical experience. 1 year of experience in DFT architecture, implementation, Automatic Test Pattern Generation (ATPG), and verification for SoCs. Preferred...Worldwide- Google in Sunnyvale, California is seeking a DFT Engineer to contribute to cutting-edge TPU technology for AI/ML applications. You will implement design-for-test methodologies and collaborate with design teams to innovate solutions. This position requires a Bachelor's...Worldwide
$300k - $350k
About the Role We are seeking an experienced Design-for-Test (DFT) Engineer to join our silicon engineering team and help stand up the DFT function alongside the architecture and physical-design (PD) teams. This is a ground-floor role on a leading-edge multi-die package...H1bVisa sponsorshipWork visa$163k - $237k
Google Inc. is seeking an experienced DFT Engineer to shape the future of AI/ML hardware acceleration in Sunnyvale, California. You will drive TPU technology that powers Google's AI/ML applications, managing the design and verification of complex digital circuits. Applicants...$138k - $198k
Google Inc. is seeking a DFT Engineer in Sunnyvale, CA to shape the future of AI/ML hardware acceleration. You will work on cutting-edge TPU technology, driving innovation that powers Google’s AI/ML applications. Responsibilities include defining DFT methodologies, implementing...Full time- Title: DFT Engineer Location: Santa Clara, California Work Type: Full Time Key Responsibilities Implement DFT solutions for Scan and MBIST architectures. Perform DFT insertion using Scan methodologies including SSN. Implement and verify MBIST repair solutions. Generate...Full time
$120k - $200k
...including hardware and software, to train and run the largest ML workloads for AGI. MatX is seeking a Silicon Design‑For‑Test (DFT) engineer to join our team as we create best‑in‑class silicon for high‑performance and sustainable GenAI. The successful candidate will be...Full timeWork experience placementLocal areaRemote workMonday to FridayFlexible hours- NVIDIA Corporation is seeking a DFT Timing Engineer in Santa Clara, California. The role involves driving timing analysis and closure for DFT logic across all NVIDIA chips at all hierarchical levels. The ideal candidate will have a BS in Electrical or Computer Engineering...
- SPACE EXPLORATION TECHNOLOGIES CORP is seeking a SR. ASIC DFT ENGINEER to develop next-generation ASICs for Starlink, enhancing global internet connectivity. The ideal candidate has a Bachelor’s degree in electrical engineering and at least 5 years of experience in semiconductor...
$136k - $218.5k
...human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's...Full time$181.1k - $318.4k
Software Engineer - Systems (DFT Initiative) Cupertino, California, United States Hardware Are you interested in working on tools and software that directly enable hardware validation? Our Hardware Test Engineering team is evolving our Design for Test (DFT) methodology...Relocation$140k - $210k
...Design Team to implement and verify advanced Design for Test/Debug techniques. The ideal candidate will have 10+ years of experience in DFT methodologies, focusing on low power, multi-voltage designs. Responsibilities include DFT pattern generation and debugging...- Purple Hires Inc is looking for a DFT Engineer located in Santa Clara, California. In this role, you will implement DFT solutions for Scan and MBIST architectures, perform DFT insertion using methodologies such as SSN, and verify DFT functionality among various key responsibilities...Full time
$196k - $310.5k
Overview Design-for-X Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions in AI for Chip Design... ...semiconductor chips. What You’ll Be Doing Innovation in DFT Power, Thermal & Voltage Noise Methodology areas. Develop low power...
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