Senior ASIC Timing Engineer — DFT & Full-Chip Closure
NVIDIA Gruppe
NVIDIA Gruppe is seeking a candidate in Santa Clara for a role focusing on timing analysis and closure for DFT logic across its chips, including GPUs, CPUs, and SoCs. The ideal candidate has a strong background in Static Timing Analysis and a minimum of 5 years of experience in Electrical or Computer Engineering. You will collaborate across teams to drive timing constraints and improve design workflows. Competitive salary range is $136,000 - $218,500 for Level 3 and $168,000 - $264,500 for Level 4, with equity options available. #J-18808-Ljbffr NVIDIA Gruppe
Vacancy posted 5 days ago
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