Senior DFT Engineer: Low-Power ASIC Test & Debug
$140k - $210kNutanix
Qualcomm is looking for an experienced candidate for the ASIC Design Team to implement and verify advanced Design for Test/Debug techniques. The ideal candidate will have 10+ years of experience in DFT methodologies, focusing on low power, multi-voltage designs. Responsibilities include DFT pattern generation and debugging simulations. The role is based in Santa Clara, California, with a competitive salary range of $140,000 to $210,000 and a comprehensive benefits package. #J-18808-Ljbffr Nutanix
Vacancy posted 1 day ago
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