Design Engineer - Timing Methodology
$143.8k - $230kBroadcom
Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:Broadcom's Timing Sign-Off group in Central Engineering is looking for an energetic and self-driven professional to join our team. Our group’s mission is to provide advanced timing sign-off methodologies to Broadcom’s chip teams with the goal of achieving best in class solutions with high yield and fully optimized margins. The candidate will participate and take ownership in Advanced Timing Sign-off methodology development and modeling for SOC and 3D/2.5D IC design. This includes complex studies and analysis of new concepts leading to design, development and improvement of existing and new solutions. The candidate should have experience in methodology development with deep knowledge of advanced silicon technologies, production testability and yield. The candidate should have Tapeout experience in high volume / high yield complex SOCs at advanced technology nodes. The candidate will be working closely with other experts across the company in a fast paced project oriented agile environment. The candidate must have the ability to prioritize well, communicate clearly, proactively deliver practical and quality solutions on-time, work well with external and internal partners, and possess advanced IC design engineering skills. The candidate will be expected to work across multiple facets of projects and juggle multiple responsibilities at the same time.Responsibilities: Develop and deploy timing signoff methodologies for advanced technology nodes.Design and implement SOC, 3D/2.5D IC & multi-die signoff solutions.Participate & Lead in EDA flow development for Primetime, Tempus & Innovus.Qualifications:The minimum engineering experience required is typically a BS degree in EE/CS with 12+ years of industry experience, or an MS degree or Ph.D. degree in EE/CS with 10+ years of industry experience.Strong hands-on experience in Timing Signoff methodology development and ownership.Strong hands-on experience in SOC and 3D/2.5D IC timing signoff. Strong hands-on experience with statistical data analysis and modeling.Strong hands-on experience in silicon technologies, testability and yield. Strong hands-on experience with industry standard STA tools such as Primetime and Tempus.Strong hands-on experience developing scripts in TCL, Python, Perl, Unix shell and flow automation.Experience with revision control, issue management/defect tracking, continuous integration, and continuous delivery/deployment tools.Strong analytical skills and extremely detail oriented, organized and methodical.Strong communication skills. Clear and concise.Strong multitasking and context switching skills.Optimistic yet pragmatic attitude.Demonstrable skills for quick ramp-up.Ability to stay calm under extreme pressure. Team player.Able to work with minimum supervision, handle ambiguity and drive problem solving to resolution autonomously. Compensation and BenefitsThe annual base salary range for this position is USD 143,800.00 To USD 230,000.00As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.SummaryLocation: USA-California-San Jose-1320 Ridder Park DriveType: Full time
$168k - $264.5k
We are now looking for a Senior CPU Design Methodology Engineer!The complexity of chip development has greatly increased over the years. We are now... ...protected by law.SummaryLocation: US, OR, Hillsboro; US, TX, Austin; US, AZ, Remote; US, CA, Santa ClaraType: Full timeSuggestedFull timeRemote work$168k - $264.5k
...world.NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer, PPA Fusion Compiler to join our outstanding Networking Silicon... ...in developing flow and tool methodologies for P&R, timing analysis and closure, convergence in IR/Signal-EM, power and...SuggestedFull time$136k - $218.5k
...world.We are now looking for a motivated Senior Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge... ...improvements, critical-path planning and crafting, or methodology/workflow improvements.Hands-on experience in block, sub-...SuggestedFull time$141.91k - $200.34k
...Description: About the RoleJoin the Design Technology Platform (DTP)... ...of physical design methodologies and drive full-chip SoC integration... ...Master's degree in electrical engineering or related field with minimum... ...allows employees to split their time between working on-site at...SuggestedFull timeWork experience placementLocal areaImmediate startShift work$168k - $264.5k
...impact on the world.We are looking for a physical design engineer to be a part of NVIDIA’s physical design (PD) methodology team driving innovation in PD across all of... ...also do it at scale, in the shortest possible time. Your work in physical design methodology directly...SuggestedFull timeRemote work$136k - $218.5k
...world.NVIDIA's Advanced Package Engineering team sits at the intersection of cutting-edge chip design and the physical reality of... ...of use.Develop flows/tools and methodologies to construct, analyze, and validate... ..., CA, Santa Clara; US, TX, Austin; US, CA, RemoteType: Full timeFull time$164.47k - $311.89k
Job Details:Job Description: As a Physical Design Timing Engineer, you will play a pivotal role in shaping the performance, power efficiency... ...of high-performance, low-power solutions while developing methodologies that enhance efficiency and operational excellence. This...Full timeInternshipLocal areaImmediate startShift work$2,000 per month
...frontier intelligence. We co-design chips, racks, software, and manufacturing... ...and staffed by leading engineers, Etched is redefining the... .... As a Physical Design Methodology Engineer, you will architect... ...speeds, directly accelerating our time-to-market and enabling PPA gains...Work at officeRelocation package- ...transport logistics, data center design and construction, equipment... ...specialized Senior Design Engineer with deep expertise in EDA tool capabilities and design methodologies to join our ASIC development... ...floorplanning, placement, routing, and timing closure methodologies....Full timeLocal area
- ## ASIC/VLSI Design EngineerAustin, Texas · Full-time#### About The PositionWe are looking for talented and experienced VLSI Design Engineers/Micro-architects.As an VLSI Digital Design Engineer... ...new EDA tools, languages, and methodologies (e.g., CDC, Linting, Formal...Full time
- ...position, you will be defining, developing, and driving timing methodologies across the Adaptive and Embedded Computing Group. You... ...closely with architecture, product planning, process, design, and product engineering teams to realize silicon solutions with best-in-class...
$168k - $264.5k
...technical depth.We're the Silicon Design for Productization (DFP) Team... ...executable productization methodology. Power and thermal are among... ...bridge. We're looking for an engineer who reasons from first... ...improve, leverage, and shorten time to market.Serve as a key technical...Full time$157.3k - $212.8k
...Acceleration team you’ll be responsible for the design and optimization of Hardware in our data... ...for block and full-chip level static timing analysis• Write, debug & validate timing... ...and teamwork with other physical design engineers as well as with the RTL/Arch. teamsBasic...Full timeLocal areaFlexible hours- AMD, Inc. in Santa Clara, CA, is hiring SMTS Silicon Design Engineer to research, design, develop, and test ASIC components and systems. You... ...Collaborate with cross-functional teams, optimize power and timing, and drive significant technical challenges from concept...
$136k - $218.5k
...boundary where architecture, design, firmware, and silicon meet reality... ...are looking for a hardware engineer who builds the methods, test... .... This tooling reduces the time from observation to root-... ...infrastructure, characterization methodologies, and bring-up playbooks that...Full timeShift work$168k - $264.5k
...Verification Infrastructure Engineer to join the SoC verification... ...tooling.Collaborate closely with design, architecture, performance,... ...best practices in verification methodology, scalability, performance... ...protected by law.SummaryLocation: US, CA, Santa ClaraType: Full timeFull time$220k - $350k
...Job Description Job Description About the role Own Full chip and Block timing methodologies and execution to-signoff of our AI accelerator silicon. Work with chip-design and software teams driving DensityAI's AI accelerator program from first silicon through scale...Full timeH1bVisa sponsorshipWork visa$136k - $218.5k
...will collaborate with Architects, ASIC Design Engineers, Low Power Engineers, Performance Engineers... ...doing:Define and implement tools and methodologies for efficient data generation from post... ...by law.SummaryLocation: US, TX, Austin; US, CA, Santa ClaraType: Full timeFull time$196k - $310.5k
...intelligence. Make the choice to join us today.Design-for-X Engineering at NVIDIA works on groundbreaking... ...DFT Power, Thermal & Voltage Noise Methodology areas.This will include working on... ...DFT topics and VLSI areas of power, timing & voltage noiseExperience in Power Analysis...Full time$106.4k - $172.15k
...our teams work from the office full time, with flexibility when it’s needed. This... ...outcomes.Job SummaryYour Career As a Design Verification engineer on the ASIC team, you will ensure... ...reliability. You will define verification methodologies, architect test benches, write test...Full timeCasual workWork at office$141.91k - $200.34k
...:Job Description: Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this... ...Foundation in simulation-based verification methodologies UVM/ABV, with exposure to formal... ...allows employees to split their time between working on-site at their assigned...Full timeLocal areaImmediate startShift work$165k - $241.4k
...Routing, and Wireless products. We design networking hardware for... ...electrical/computer science/computer engineering/related degree and 7+ years... ...processes, debugging, methodology, and tools.Experience in verifying... ...Cisco for defined periods of time.U.S. employees are eligible...Full timeTemporary workLocal areaWorldwideFlexible hours$151k - $251.8k
...with us!Role and ResponsibilitiesAs a Design Verification Engineer, you will contribute to the... ...testbench architecture, and knowledge in methodologies across both block- and top-level environments... ...assistance (after 6 months), paid time off, student loan program, wellness incentives...Hourly payFull timeRelocation- ...your job. Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the... ...junior team members, and contribute to methodology improvementsStrong background with... ...initiative and drive for resultsStrong time management skills that enable on-time...Local area
$167.7k - $245.2k
...grow. Because full product development—from design to qualification to production—is within... ...and strategy for ASIC verification methodology and execution across multiple programs and... ...employment with Cisco for defined periods of time.U.S. employees are eligible for paid time...Full timeTemporary workLocal areaFlexible hours$120k - $192k
Please Note:1. If you are a first time user, please create your candidate login... ...:Broadcom is looking for a Silicon Design and Validation Engineer. In this highly visible role, you... ...circuitry.Knowledge of development methodologies, design flows including EDA integration...Full timeLocal area- ...cloud, and AI. Whether you’re designing next-gen processors, enabling... ...design verification engineer to join our growing team. As... ...engineers located in different sites/time zones. You have strong analytical... ...in design flow, verification methodology and general computational...
- NVIDIA Corporation in Santa Clara, CA is seeking a Senior CPU Design Methodology Engineer to lead system-level methodologies for SOC creation and front-end design quality. You will help define scalable processes, automate RTL integration, and collaborate with ASIC, Physical...
- NVIDIA is seeking a Senior Software Engineer for SOC design methodology in Santa Clara. You will architect automated data flows, collaborate on specifications, and build scalable data preprocessing pipelines for graph-scale data using C++ and Python. You will develop tools...
- A leading technology firm is seeking a Sr. Design Engineer in Santa Clara, CA. The ideal candidate will have 7-8 years of experience in design... ...The role requires proficiency with tools like CDC, SYN, and Timing closure, as well as experience with multiple clock domains...
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