Remote SV/UVM Verification Engineer | Long-Term Contract
Correct Designs
Austin, TX
- Remote job
Correct Designs in Austin, TX is seeking a talented Design Verification Engineer to ensure the quality of complex design blocks. This role supports advanced CPU/GPU based SOCs across various industries. Candidates should have at least 3 years of experience in verification, proficiency in SystemVerilog and UVM methodologies, and strong analytical skills. The position offers long-term contracts, remote options, and benefits such as health care and retirement plans. #J-18808-Ljbffr Correct Designs
Vacancy posted 4 days ago
Similar jobs that could be interesting for youBased on the Remote SV/UVM Verification Engineer | Long-Term Contract in Austin, TX vacancy
- Design Verification Engineer Looking for new challenges? Would... ...the variety of a contract position along with long‑term stability and benefits... ...System Verilog UVM experience to work... ...long‑term contracts, remote or in‑person work,... ...blocks using advanced SV/UVM verification...Long term contractRemote workContract work
- CxDesign, LLC is seeking a seasoned ASIC & FPGA Verification Engineer to write and debug testbench components, tests, assertions, and functional... ...must have over 10 years of experience preferably in a UVM/SV environment. This role requires U.S. citizenship due to security...Suggested
- microTECH Global Limited is seeking an ASIC Verification Engineer for a 6-month contract, which can be performed remotely. The role requires a strong background in verification... ...of ASIC/SoC systems, and proficiency in UVM/SystemVerilog-based verification. This position...Remote jobContract workImmediate start
- A leading nonprofit research organization in Cambridge, MA is seeking a motivated Senior UVM Digital Verification Engineer to tackle verification challenges in FPGAs and ASICs. This role requires collaboration across multidisciplinary teams to apply modern verification...Remote job
- A leading provider of 4G and 5G network solutions is seeking a UVM SystemVerilog Verification Engineer to join their team in Texas or a remote capacity. The role involves developing and executing verification plans, ensuring compliance with specifications. Candidates should...Remote job
- ...looking for a Senior Design Verification Engineer with over 8 years of... ...particularly in SystemVerilog and UVM methodologies. The role... ...fields. Candidates can expect a contract role with long-term opportunities in Austin, TX, and potentially remote work. Benefits include...Remote jobContract work
- Location: Warren, New Jersey, Plano, TX or REMOTE U.S. Company: AirSpan Networks About AirSpan AirSpan Networks is... ...industrial applications. We are looking for a skilled UVM SystemVerilog Verification Engineer to join our dynamic team and contribute to the validation...Remote work
- Senior UVM Digital Verification Engineer page is loaded **Senior UVM Digital Verification Engineer**remote typeRemote Available locationsCambridge, MARemote (US Only) time typeFull time posted onPosted Today job requisition idJR000159 **Overview:**Draper is an independent...Remote workLocal area
- A leading semiconductor company in Santa Clara, California, is looking for a Verification Engineer to enhance SystemVerilog/UVM-based testbenches for their Infinity Fabric network. Ideal candidates will have significant experience verifying design blocks and a strong background...
- Job Description Job Title: ASIC Verification Engineer Job Type: Contract Duration: 6 months initial plus possible extension Location: Munich/Remote - 100% remote working Start: ASAP About... ...Good knowledge of ASIC/SoC Systems UVM/SystemVerilog‑based Verification...Remote workContract workImmediate start
- Talascend is seeking a Sr. Safety Verification and Validation Engineer for a long-term (12 month) contract-to-direct role with our Nuclear Energy client based in Bellevue, WA. Fully remote is possible, but preference will be given to local candidates, willing to work in...Long term contractRemote workWork at officeLocal areaRelocation package
$107.5k - $204.5k
...is seeking talented engineers to support critical programs... ...a Principal Firmware Verification Engineer, you will... ...Methodology (UVM) Experience in both System... ...as on-site, hybrid or remote. The salary range for... ...insurance, short-term disability, long-term disability, 401(...Remote workFull timeTemporary workWork experience placementWork at officeWorldwideRelocation packageFlexible hours$150k - $225k
...Description Job Description Senior Verification Engineer Also open to staff,... ...of a sign-on bonus Hybrid Remote: 3 days in the office per... ...Developing, driving, and implementing UVM SystemVerilog TestBench... ...stimulus covering, SV assertions, and scripts as necessary...Remote workWork at officeRelocation packageCypress HCM
Suwanee, GA24 days ago- Senior Design Verification Engineer Looking for new challenges... ...the variety of a contract position along with long term stability and benefits... ...System Verilog UVM experience to work... ...both in‑person and remote work. Whether you... ...using equally complex SV/UVM verification environments...Remote workHourly payContract workTemporary work
$175 per hour
...Position: RTL Design Engineers Type: Contract Compensation: $1... ...hour Location: Remote Duration: 3+... ...Collaborate with architecture, verification, and implementation... .../SystemVerilog and UVM . ~ Solid... ...formal verification or SV/UVM-based design verification...Remote jobHourly payWeekly payContract workFor contractorsSummer workMercor
New York, NY4 days ago$115 per hour
...digital chip design and verification professionals with... ...frontier silicon engineering workflows. This... ...and upcoming remote consulting opportunities... ...SystemVerilog, UVM, reusable... ...formal verification, SV/UVM-based verification... ...compensation Contract Details Independent...Remote jobHourly payWeekly payJob sharingFull timeContract workPart timeFor contractors24-MAG
New York, NY21 days ago$105.65k - $200.34k
...technology firm in Austin, Texas is seeking a motivated CPU Verification Engineer. The role involves validating CPU logic designs using robust... ...Engineering or a related field, with experience in SystemVerilog and UVM-based testbenches. The position offers a competitive salary...$75k - $150k
A nonprofit research and development organization in Cambridge, MA, is seeking a motivated UVM Digital Verification Engineer. The role involves tackling verification challenges within FPGAs and ASICs. Candidates should have 3-5 years of experience or relevant master's experience...- A leading research and development firm in Cambridge, MA is seeking an experienced UVM Digital Verification Engineer to innovate digital and mixed-signal designs. The role involves designing circuits, developing verification plans, and contributes to complex hardware solutions...
- ...technology company in Austin is seeking an experienced ASIC Verification Engineer to work on system-level IP projects. Candidates should have a... ...verification methodologies, with expertise in System Verilog and UVM. This position offers a competitive salary based on...
- ...View is seeking an experienced validation engineer to develop custom silicon solutions that... ...role involves planning and executing verification activities, ensuring design accuracy while... ...possess significant experience with UVM and SystemVerilog, complemented by advanced...
- ...Job Description Job Description We're looking for a Senior Verification Engineer to play a key role in verifying complex SoC and subsystem... ...and define verification requirements. Develop and maintain UVM-based verification environments. Create detailed test plans...Remote job
FortifyIQ
Salem, MA9 days ago - ...Job Description Job Description Role: ASIC Verification Engineer - ARM Location: Remote Job Type: Contract Interview: Phone/Skype Job Description... ...reviews, Verification plans, test case development, UVM environments, Coverage (analysis), Debugging, GLS...Remote jobContract work
PDDN INC.
Santa Clara, CA14 days ago - ...Oracle. THE PERSON We are seeking a high‑impact MTS Design Verification Engineer with strong technical depth, ownership, and the ability to drive... ...Architecture & Testbench Development Develop robust UVM‑based testbench architectures for IP, subsystem, and SoC‑level...
- ...Job Description Job Description Senior ASIC Verification Engineer (AI Hardware) — Remote (U.S.) — No Visa Sponsorship Overview Our client an AI... ...scalable verification environments using System Verilog and UVM Create simulation infrastructure, including...Remote workVisa sponsorship
4 Staffing Corp
San Jose, CA17 days ago $138k - $198k
Google Inc. is seeking a Verification Engineer in Mountain View, CA. In this role, you’ll verify complex digital design blocks, utilizing SystemVerilog and UVM to enhance verification environments and ensure functionally correct designs. The qualified candidate will have...- An established industry player is seeking a skilled verification engineer with extensive experience in UVM and SystemVerilog. This role involves defining and implementing a comprehensive verification environment, writing test plans, and debugging RTL and gate-level netlists...
- ...Senior Firmware Verification Engineer Job Description Renesas Electronics America is seeking... ...Preferred Qualifications Experience with UVM or other structured verification... ...and global support system, including the remote work option and Employee Resource Groups...Remote workLocal areaFlexible hours
Renesas
Austin, TX1 day ago - ...Job Description Job Description We're seeking a Verification Engineer to contribute to the validation of advanced chip designs. You'll help create and maintain UVM environments, write tests, and ensure functional coverage for high-performance silicon products. The...Remote job
FortifyIQ
Salem, MA9 days ago - A leading tech firm in Redmond seeks an experienced verification engineer to define and implement UVM environments. Candidates must have over 10 years of experience in UVM testbench development, block level verification, and RTL debugging. The role includes creating test...
Do you want to receive more vacancies?
Subscribe and receive similar vacancies to Remote SV/UVM Verification Engineer | Long-Term Contract. Be the first to apply!
Related searches
- senior design verification engineer Austin, TX
- soc design verification engineer Austin, TX
- validation specialist Austin, TX
- verification & validation engineer Austin, TX
- senior verification engineer Austin, TX
- verification engineer Austin, TX
- senior validation engineer Austin, TX
- system verification engineer Austin, TX
- design verification engineer Austin, TX
- validation engineer Austin, TX