Senior Verification Engineer - UVM, SoC Memory & PCIe
Tara Technical Solutions (TTS)
A leading semiconductor firm in San Jose is seeking a Design Verification Engineer responsible for verifying complex designs. The ideal candidate will have significant experience designing test benches and a strong grasp of verification methodologies like UVM. A Bachelor's degree with relevant experience is required. Competitive salary and benefits are offered, including health insurance and 401(k). #J-18808-Ljbffr Tara Technical Solutions (TTS)
Vacancy posted 2 days ago
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