Average salary: $114,363 /yearly

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  • $143.3k

     ...across all industries. We are seeking experienced Hardware Design Engineers to work with partners and vendor and build the next...  ...performance at low cost. Key job responsibilities - Develop formal verification plans, implement and verify state-of-the-art IP architectures... 
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    Local area
    Work from home

    Annapurna Labs Inc.

    Cupertino, CA
    4 hours agonew
  •  ...A leading technology company is seeking an ASIC Design Verification Engineer to optimize low latency SoCs for critical applications. The ideal candidate will have extensive experience in design verification, UVM, and a strong background in programming. In this role, you... 
    Suggested
    Full time

    SQL Pager LLC

    San Francisco, CA
    15 days ago
  • $181.1k - $318.4k

    A leading technology company in San Francisco seeks a PHY Design Verification Engineer to join its wireless silicon development team. The role involves pre-silicon RTL verification of wireless PHY and its interfaces, requiring advanced knowledge in Verilog and SystemVerilog... 
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    Full time

    Apple Inc.

    San Francisco, CA
    15 days ago
  •  ...A leading tech company is seeking an ASIC Design Verification Engineer I in San Francisco, CA. You will work collaboratively with a talented team on innovative communications and network processing silicon. Candidates should have recent or current Bachelors degree studies... 
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    Full time

    Cisco

    San Francisco, CA
    4 days ago
  • $129.8k

     ...cloud that powers hundreds of thousands of businesses in 190 countries around the world. We are seeking an experienced Design Verification Engineers to build the next generation of our cloud server platforms. Our success depends on our world-class infrastructure; we’re... 
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    Local area
    Work from home

    Annapurna Labs Inc.

    Cupertino, CA
    4 hours agonew
  •  ...Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques...  ...UVM ○ Debug RTL and Gate simulations and work with design engineers to verify fixes. ○ Write diagnostics for validation of FPGA... 
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    Mirafra Technologies

    San Jose, CA
    4 days ago
  •  ...OpenAI is developing custom silicon to power the next generation of frontier AI models. Were looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in... 
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    Full time

    OpenAI

    San Francisco, CA
    15 days ago
  • $126.8k - $190.9k

     ...all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/...  ...and design, VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description... 
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    Full time
    Relocation

    Apple Inc.

    San Francisco, CA
    15 days ago
  •  ...A leading technology company in San Francisco is seeking a highly skilled design verification engineer to ensure bug-free first silicon for new products. The role involves developing methodologies for verification, creating test plans, and utilizing advanced tools and... 
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    Full time

    Apple Inc.

    San Francisco, CA
    15 days ago
  •  ...Title Design Verification Engineer Internal IP Location Bay Area (hybrid) or Toronto About the Company A fast-growing AI startup designing next-generation compute hardware. The company specializes in building high-performance IP blocks and accelerators... 
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    Full time

    Amadeus Search

    San Francisco, CA
    5 days ago
  •  ...ASIC Design Verification Engineer Client Overview Our client is building the first latency optimized SoC for their industry. Using its proven AI accelerator designs, we are targeting best in class latency with order of magnitude improvements for years to come. Low... 
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    Full time
    Night shift

    SQL Pager LLC

    Sunnyvale, CA
    15 days ago
  • $190k - $265k

     ...Join to apply for the Design Verification Engineer role at Eridu AI Join to apply for the Design Verification Engineer role at Eridu AI Get AI-powered advice on this job and more exclusive features. This range is provided by Eridu AI. Your actual pay will... 
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    Full time

    Eridu AI

    San Francisco, CA
    15 days ago
  • $147.4k - $272.1k

     ...challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that... 
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    Full time
    Work experience placement
    Relocation

    Apple Inc.

    San Francisco, CA
    6 days ago
  •  ...A leading technology company seeks a hardworking design verification engineer in San Francisco. This role includes developing test plans and methodologies to ensure bug-free silicon for cutting-edge products. Candidates should have a BS degree with at least 3 years of... 
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    Full time

    Apple Inc.

    San Francisco, CA
    6 days ago
  •  ...independent training company serving the semiconductor design and verification marketplace. This fast growing yet boutique style training...  ...and then effectively engage an audience and present complex engineering topics. This is no ordinary engineering role, but rather... 
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    Full time

    EDA CAREERS, (Technology Futures Inc).

    San Francisco, CA
    6 days ago
  •  ...ASIC Design Verification Engineer I (Full Time) United States Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly... 
    Full time

    Cisco

    San Francisco, CA
    4 days ago
  • $140k - $225k

     ...Tara Technical Solutions Recruiting for a Principal ASIC Verification Engineer role. Principal ASIC Verification Engineer San Jose Fulltime, direct hire with a Fortune 500 client. Pay range: $140,000 $225,000 per year (actual pay based on skills and experience... 
    Full time
    Work experience placement

    Tara Technical Solutions (TTS)

    San Francisco, CA
    3 days ago
  • $195k - $265k

     ...0/yr - $265,000.00/yr Key Responsibilities Specialized Verification Strategy: Develop verification infrastructure and test cases...  ...thoroughness of the test suite. Offer actionable feedback to design engineers, focusing on identifying gaps and suggesting enhancements to... 
    Full time

    Eridu

    San Francisco, CA
    11 days ago
  •  ...A leading tech company in San Francisco seeks a Design Verification Engineer to develop verification methodologies and plans, ensuring the functionality of complex hardware designs. You will work closely with various engineering teams and require a strong background in... 
    Full time

    Amazon

    San Francisco, CA
    2 days ago
  •  ...One of our leading client is looking for Design Verification Engineer in Sunnyvale CA Key Responsibilities: Strong understanding of SV and UVM and good debugging skills. Understanding of AMBA protocols. Understand design specs and develop test plans based... 
    Part time

    Programmers.io

    Sunnyvale, CA
    1 day ago
  •  ...As a Design Verification (DV) Engineer, you will be part of an advanced architecture team that is exploring new hardware designs to improve our devices. In this role, you will be responsible for defining the verification methodology and implementing the corresponding... 
    Full time

    Amazon

    San Francisco, CA
    2 days ago
  •  ...Job Title: Verification Engineer (SystemVerilog/UVM)&##128205; Location: Sunnyvale, CA or Austin, TX ~514 years experience Responsibilities Develop and maintain UVM/SystemVerilog-based verification environments for IP, subsystem, and SoC-level testing.... 
    Part time

    Globex Digital

    San Diego, CA
    1 day ago
  •  ...challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that... 
    Full time
    Work experience placement

    Apple Inc.

    San Francisco, CA
    15 days ago
  •  ...and AI chip startups. They operate at the cutting edge of AI and semiconductor design. They are seeking an experienced Design Verification Engineer with expertise in UVM. Their focus is on building verification platforms using LLMs to automate and accelerate chip... 
    Full time

    EDA CAREERS, (Technology Futures Inc).

    San Francisco, CA
    15 days ago
  •  ...nextgeneration performance and efficiency across highly complex hardware and software ecosystems. They are seeking a Design Verification Engineer with deep expertise in SystemVerilog/UVM and digital ASIC verification. This role is critical for ensuring robust, reusable... 
    Full time
    Worldwide

    Quix Recruitment Group Ltd

    San Francisco, CA
    15 days ago
  • $140k - $225k

     ...A leading technical solutions provider is recruiting for a Principal ASIC Verification Engineer in San Francisco. This full-time role with a Fortune 500 client requires substantial experience, including verifying designs and fluent knowledge of RTL verification methodologies... 
    Full time

    Tara Technical Solutions (TTS)

    San Francisco, CA
    3 days ago
  • $85.85k - $116.15k

     ...Find your future with us. Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC/FPGA Verification Engineers (Associate, Experienced, or Lead) to join us as part of our Boeing Electronic Products team in either El Segundo or... 
    Permanent employment
    Work experience placement
    Interim role
    Relocation
    Visa sponsorship
    Work visa
    Flexible hours
    Shift work
    Day shift

    Boeing

    El Segundo, CA
    2 days ago
  •  ...Job Description: We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionality, performance, and reliability. You... 
    Part time

    Neutrino Advisory, an Inc 5000 Company

    Mountain View, CA
    1 day ago
  • $195k - $265k

     ...A Silicon Valley hardware startup seeks a Mid-Senior ASIC Verification Engineer to lead verification strategies for innovative AI networking technology. The role involves developing ASIC test cases, ensuring compliance with standards, and delivering coverage analysis.... 
    Full time

    Eridu

    San Francisco, CA
    11 days ago
  •  ...An innovative startup at the forefront of AI and semiconductor design is seeking a Design Verification Engineer with expertise in UVM. This role offers the opportunity to work on cutting-edge technologies that automate chip development using AI. As part of a small, elite... 
    Full time

    EDA CAREERS, (Technology Futures Inc).

    San Francisco, CA
    6 days ago