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Lead design architect - architecture

Doist

Architect is seeking a founding member of the Technical Staff to own the AI-driven memory subsystem RTL. You will define block-level micro-architecture for memory controllers, hierarchy, and accelerators to maximize bandwidth and minimize latency for ML workloads.
You will collaborate with DV, SW, and ML teams, prototype on FPGA, and guide verification with memory timing models and BFMs. A strong background in DDR5/HBM protocols and high-frequency controller design is essential.

#J-18808-Ljbffr Doist

Vacancy posted 3 days ago
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