Sign up to access all features of our service.
  • Job search
  • Favorites
  • Create a CV
    New
  • Salaries
  • Subscriptions

ASIC Design Engineer - Pixel IP DMA

$150.4k - $277.6k

Apple Inc.

Cupertino, California, United States Hardware

Do you love creating sophisticated solutions to highly complex challenges? As part of our Hardware Technologies group, you’ll help design our next-generation, high-performance, power-efficient system‑on‑chips (SoCs). You will ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices! In this highly visible role, you will be at the center of the Pixel IP design effort in pixel processing. You will collaborate with all teams, making a critical impact getting functional products to millions of customers quickly.

Description

As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that coordinate moving large amounts of data between the memory system and the Pixel IP Engine. In this front-end design role, your tasks will include:

  • Exploring solutions to enhance performance while minimizing power and area
  • Detailing specifications and building RTL designs
  • Working with design verification and formal verification teams to verify functionality and performance

Minimum Qualifications

  • Bachelors Degree + 3 years of experience

Preferred Qualifications

  • Experience in multimedia IP/SoC front-end ASIC RTL design
  • Tight-knit collaboration skills with excellent written and verbal communication skills
  • Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug designs
  • Previous experience designing dedicated DMA engines (especially related to machine learning applications), data storage, memory controllers, networking, image processing, and/or interconnects
  • Good understanding of arbitration, address translation, caching, on-chip interconnects, and performance analysis
  • Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB)
  • Experience in front-end implementation tasks such as synthesis, area and power analysis, linting, and logic equivalence checks

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 and $277,600, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.

#J-18808-Ljbffr

Vacancy posted 1 day ago
Similar jobs that could be interesting for youBased on the ASIC Design Engineer - Pixel IP DMA in Sunnyvale, CA vacancy
  • Apple in Sunnyvale is seeking a seasoned hardware design engineer to contribute to next-generation Pixel IP ANE. You will design RTL for high-speed subsystems and...  ...in EE/CE with 10+ years of hands-on experience in ASIC/SoC design, strong AMBA knowledge, and proficiency... 
    Suggested

    Apple

    Sunnyvale, CA
    2 days ago
  • $150.4k - $277.6k

     ...part of our Hardware Technologies group, you’ll help to design our next-generation Apple Neural Engine. You will work on designs that will contribute to the...  ...to Apple products. Description As part of the Pixel IP ANE design and integration engineer in pixel IP team,... 
    Suggested
    Relocation package

    Apple Inc.

    Sunnyvale, CA
    1 day ago
  • $216.2k - $394k

     ...ASIC Design Engineering Lead - SoC IP DMA In this highly visible, hands-on role, you will lead a team of engineers at the center of Apple's SOC IP DMA design effort. Balancing equal parts people management and technical leadership, you will guide your team through the... 
    Suggested
    Worldwide
    Relocation

    Apple Inc.

    Sunnyvale, CA
    21 hours ago
  • Apple Inc. in Sunnyvale seeks an experienced ANE design/integration engineer to advance RTL designs for high-speed subsystems within the Pixel IP ANE team. You will collaborate with architecture, verification, power, and physical design groups to ensure robust performance... 
    Suggested

    Apple Inc.

    Sunnyvale, CA
    1 day ago
  • $184.7k - $324.8k

     ...Hardware Technologies group, you’ll help design our next-generation, high-performance,...  ..., you will be at the center of the Pixel IP design effort to capture and display beautiful...  ...quickly. Description As an ASIC Design Engineer in the Pixel IP design team, you be... 
    Suggested
    Relocation

    Apple Inc.

    Sunnyvale, CA
    1 day ago
  • $116k - $189.75k

    The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip. The clocks team interacts... 
    Full time
    Work experience placement

    Nvidia

    Santa Clara, CA
    2 days ago
  • $168k - $264.5k

    We are now looking for a Senior ASIC Design Engineer.NVIDIA is seeking ASIC Design Engineers to implement...  ...your tasks.Work on a broad list of IPs such as GPU's work scheduler, time distribution...  ...system, interrupt controllers, and DMA engines.Architect features to help... 
    Full time
    Work experience placement

    Nvidia

    Santa Clara, CA
    5 days ago
  • $167k - $275k

     ...providing a unique combination of design, development, and fabrication...  ...-generation processor and SoC IP solutions. This role provides...  ...for a team of digital design engineers, driving architecture...  ...subsystems, SoC integration, ASIC design flow, Synthesis and timing... 
    Local area

    MIPS Holding Inc

    Santa Clara, CA
    3 days ago
  • $128k - $316.8k

     ...ASIC Design Engineer Graduate (Video Silicon IP) - 2027 Start Location: San Jose Team: Technology Employment Type: Regular Job Code: A178830 Share this listing: Responsibilities About the teamOur team is building industry-leading, highly... 
    Temporary work
    Local area

    ByteDance (old)

    San Jose, CA
    1 day ago
  • $280k

    Job title: ASIC Design Engineer, RTL (Senior/Staff/Principal)Location: San Jose, CA or Colorado Springs, CO (on-site)Salary: $280k-580k total compHelp...  ..., and low-power techniques.- Integration: Bring third-party IP into your blocks and make sure it works smoothly with the... 

    CyberCoders

    Sunnyvale, CA
    4 days ago
  • $116k - $189.75k

     ...innovative technology and dedication to excellence guide us. As an ASIC Design Engineer, you will build powerful SoC and GPU products. These products...  ...deliver world-class RTL builds.Working on a diverse list of IPs, including GPU's time distribution system, engine scheduler,... 
    Full time
    Work experience placement

    Nvidia

    Santa Clara, CA
    5 days ago
  • $175k - $215k

     ...ASIC Design Verification Engineer Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since...  ...Evaluate, integrate, and verify third-party Verification IP (VIP) to accelerate the development cycle Define and analyze... 
    Full time
    Remote work

    Waymo

    Mountain View, CA
    4 days ago
  • $150k - $250k

    Job Title: Senior ASIC Design EngineerJob Location: Santa Clara, CA or Boston, MACompensation:...  ...seeking a highly skilled Senior ASIC Design Engineer to lead the design and development of...  ...and compliance with standards.Engage in IP design and integration, focusing on Ethernet... 

    CyberCoders

    Santa Clara, CA
    3 days ago
  • $168k - $264.5k

    We are now looking for a Senior ASIC Design Engineer to join our DFT team!NVIDIA has continuously reinvented itself over two decades. Our invention...  ..., design, implementation, and verification of DFT IPs for our next-generation SoC products. You’ll help drive innovation... 
    Full time

    Nvidia

    Santa Clara, CA
    3 days ago
  • $156.4k - $253k

     ...About the Role Join our ASIC team and help deliver the digital...  ...platforms. You will own module design from specification through...  ...verification and physical‑design engineers to hit aggressive performance,...  ...integrating, and configuring complex IP blocks for high‑speed... 
    Full time
    Work at office

    Palo Alto Networks, Inc.

    Santa Clara, CA
    4 days ago
  • $200k - $290k

     ...inference.About The Role:As a senior front-end design engineer, you will be a key part of the world-...  ...End Chip integration and third-party IP integration.Demonstrated experience in high...  ...Analysis is a plus.Experience managing external ASIC vendor through product development cycle.... 
    Remote work

    Cerebras Systems

    Sunnyvale, CA
    3 days ago
  • $167k - $275k

     ...service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s...  ...more information, visit Summary of Role: The PMTS Digital Design Engineer will lead the architecture implementation, microarchitecture... 
    Full time
    Local area

    Globalfoundries

    Santa Clara, CA
    3 days ago
  •  ...your career. THE ROLE: You will contribute to the ASIC (chip) design for high-performance network chips: AINIC and...  ...team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.THE PERSON... 
    Night shift

    AMD

    Santa Clara, CA
    1 day ago
  • Synopsys, Inc. in Sunnyvale seeks an experienced ASIC digital design engineer with RTL ownership to deliver production RTL for LPDDR PHY IP across mobile and AI applications. You will optimize timing, power and area across multiple process nodes, develop Perl automation... 

    Synopsys, Inc.

    Sunnyvale, CA
    1 day ago
  •  ...revolutionary satellite communications network designed to deliver symmetrical data speeds of...  ...worldwide. Principal Modem PHY IP Design Verification Engineer This role is responsible for...  ...delivery for next-generation wireless ASIC platforms. The ideal candidate combines... 
    Worldwide

    Blue Origin

    Cupertino, CA
    2 days ago
  • $140k - $229.8k

     ...Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:As a...  ...chip sets and is seeking Hardware Design engineers with solid ASIC design experience...  ..., Design, Validation, IP development, Synthesis, Timing closure... 
    Work experience placement
    Work from home

    Qualcomm

    Santa Clara, CA
    5 days ago
  • $168k - $264.5k

     ...seeking a Senior Custom SOC/IP Verification Engineer to verify the next generation...  ...requires a skilled ASIC Verification Engineer with expertise...  ...connectivity across complex SoC designs. This position demands a...  ...chip integration, covering DMA, routing, arbitration, ordering... 
    Full time
    Night shift

    Nvidia

    Santa Clara, CA
    4 days ago
  • $98.6k - $133.4k

    ASIC/FPGA Design and Verification Engineer - Space Electronics - MTV (Associate, Experienced, or Lead)Company:The Boeing CompanyBoeing Space, Intelligence...  ...high-performance custom processors using the latest ARM IP to enable high-integrity, low SWAP-C flight computers. We... 
    Permanent employment
    Full time
    Work experience placement
    Interim role
    Relocation
    Visa sponsorship
    Work visa
    Flexible hours
    Shift work
    Day shift

    Boeing

    Mountain View, CA
    5 days ago
  • $163k - $236k

     ...verification of complex digital design blocks by understanding the...  ...specification and interacting with design engineers to identify important...  ...using SystemVerilog/UVM for ASICs.Preferred qualifications:Master...  ...and verifying interconnect IPs.In this role, you’ll work to shape... 
    Worldwide

    Google

    Sunnyvale, CA
    3 days ago
  •  ...We are seeking a high‑impact Design Verification Engineer with strong technical depth,...  ...complex, high‑performance ASIC designs.The ideal candidate...  ...verification efforts across IP, subsystem, and SoC levels.You...  ...as PCIe, AXI, Ethernet, DDR, DMA engines, or similar data‑... 

    AMD

    Santa Clara, CA
    2 days ago
  • $98.6k - $133.4k

    ASIC/FPGA Design and Verification Engineer - Space Electronics - MTV (Associate, Experienced, or Lead) Company: The Boeing Company Boeing Space, Intelligence...  ...high-performance custom processors using the latest ARM IP to enable high-integrity, low SWAP-C flight computers.... 
    Permanent employment
    Work experience placement
    Interim role
    Relocation
    Visa sponsorship
    Work visa
    Flexible hours
    Shift work
    Day shift

    Boeing Company

    Mountain View, CA
    2 days ago
  •  ...revolutionary satellite communications network designed to deliver symmetrical data speeds of...  .... We are seeking a Principal Modem PHY IP Design Engineer to support the design and development...  ...-generation high-performance wireless ASIC solutions. The ideal candidate brings... 
    Worldwide

    Blue Origin

    Cupertino, CA
    1 day ago
  • GlobalFoundries in Santa Clara, CA is seeking a PMTS Digital Design Engineer to drive architecture implementation, microarchitecture development, and RTL design of high-performance processor cores and subsystems. You will partner with architecture, verification, physical... 

    GlobalFoundries

    Santa Clara, CA
    1 day ago
  • Tensordyne, a Sunnyvale-based AI system solutions company, seeks a Sr ASIC engineer to lead microarchitecture and RTL implementation for high‑performance AI accelerators. You will collaborate with CPU/IP teams, drive timing closure, power optimization, and silicon... 

    Tensordyne

    Sunnyvale, CA
    1 day ago
  •  ...in Santa Clara, CA, seeks a Senior Digital Design Engineer for its NVLink Fusion AI infrastructure SoC...  ...delivering verified RTL, trade-off analysis, and IP integration. A bachelor's or master's in EE/CE with 5+ years of relevant ASIC experience and experience with #J-18808-... 

    NVIDIA

    Santa Clara, CA
    21 hours ago

Do you want to receive more vacancies?

Subscribe and receive similar vacancies to ASIC Design Engineer - Pixel IP DMA. Be the first to apply!