RTL Design Engineer

Job Description Digital Design Engineering/RTL Design Services. Architecture and microarchitecture of System on a Chip (“SOC”) subsystems, Intellectual Property Functional Blocks (“IPs”), sub-IPs, modules, and library components. Digital design using System Verilog and/or Verilog RTL, RTL generators (in Python), and/or high-level synthesis (“HLS”). RTL integration of SoC subsystems, IPs, sub-IPs, modules, and library components; SoC-level integration. Support mapping of RTL on Zebu and HAPS for IP bring up and E2E validation. Design for low power and power intent using Unified Power Format (“UPF”). Constraint development, synthesis, timing closure, and optimization of the design. Code quality checks, including Linting, Clock Domain Crossing, Reset Domain Crossing. Debug and bug fixes. Mandatory Skills VLSI Physical Place and Route. Experience 8–10 Years. Compensation Expected compensation ranges from $100,000 to $180,000. Compensation will depend on location, wages, skills, and experience. Benefits Eligible for Wipro's standard benefits, including medical and dental options, disability insurance, paid time off (including sick leave), other paid and unpaid leave options. EEO Statement Wipro provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws. Applications from veterans and people with disabilities are explicitly welcome. #J-18808-Ljbffr Wipro