RTL Engineer, Networking ASIC
$210k - $275kEridu Corp.
Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI . Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.
The company’s solutions and value proposition have been widely validated by leading hyperscalers.
Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.
Visit our website eridu.ai to learn more.
Position Overview
We are seeking experienced RTL designers to help define and implement our industry-leading Networking ASIC’s. If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking chips.
Responsibilities
- Packet buffering, queuing, and scheduling: Work on micro architecture and design implementation of high-speed networking ASIC’s, focusing on latency optimization and quality of service (QoS) support. Prior experience with on-chip memory subsystem and scheduling / arbitration design.
- Implementation and Testing: Implement designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks. Work with verification team to conduct thorough testing and validation to ensure functionality and reliability.
- Performance Optimization: Analyze and optimize pipelining architectures to improve performance metrics.
- Protocol Support: Provide support for various networking protocols such as Ethernet and IP protocols, and high speed interconnects such as UCIe.
- Troubleshooting and Debugging: Investigate and resolve complex issues related to packet queuing, working closely with cross-functional teams, including system architects, hardware engineers, and firmware developers.
Qualifications
- ME/BE with a minimum of 8-15 years of experience.
- Hands-on knowledge of SystemVerilog and Verilog is mandatory .
- Solid understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjustments.
- Proven expertise in designing and optimizing scheduling and QoS mechanisms.
- Experience with Ethernet and IP protocols.
- Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues.
- Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences.
Why Join Us?
At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.
The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
Notice to Recruiting Agencies
Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.
The pay range for this role is:
210,000 - 275,000 USD per year (San Francisco Bay Area)
#J-18808-Ljbffr$210k - $275k
...is in execution mode and has a world-class engineering team with decades of experience in state‑of‑... ...Position Overview We are seeking experienced RTL designers to help define and implement our industry‑leading Networking ASICs. As part of the Design Group, you will be...Suggested$210k - $275k
...a Silicon Valley hardware startup, seeks seasoned RTL designers to shape and implement Networking ASICs. You will specify, architect, and productize high‑speed... ..., focusing on latency and QoS. Join a world‑class engineering team advancing AI data centers and hardware...Suggested- ...startup accelerating AI data centers with industry-leading Networking ASICs. We seek experienced RTL designers to define, specify, architect, execute, and... ...interoperability, collaborating with system architects, hardware, and firmware engineers. #J-18808-Ljbffr Eridu Corp.Suggested
$213k - $287.5k
...emergent technologies. We’re looking for an ASIC Design Eengineer to help us trail-blaze... ...performance, area and power efficient RTL to achieve design targets and specifications... ...that help our team members develop your engineering expertise so you feel empowered to take on...SuggestedLocal areaFlexible hours$176.6k - $247.3k
...emergent technologies. We’re looking for an ASIC Design Eengineer to help us trail-blaze new... ....Key job responsibilitiesAs an ASIC Design Engineer, you will:• Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and...SuggestedLocal areaWork from homeFlexible hours$200k - $290k
...:As a senior front-end design engineer, you will be a key part of the... ...role requires deep expertise in RTL design and integration, with a... ...with external vendors.Networking stack experience including TCP... ....Experience managing external ASIC vendor through product development...Remote work$280k
Job title: ASIC Design Engineer, RTL (Senior/Staff/Principal)Location: San Jose, CA or Colorado Springs, CO (on-site)Salary: $280k-580k total compHelp design the chips that move the world's AI data.Every AI model trained in a hyperscale data center depends on silicon that...- ...ASIC RTL Design Engineer Responsible for microarchitecture and RTL design of high performance data processing chip. Micro-architecture definition, writing micro-architecture specifications. Write high performance and low power Verilog RTL, synthesis and timing closure...
- ...Clara, CA, is seeking a senior power analysis engineer to develop and deploy methodologies to measure... ...measurement infrastructure across architecture and RTL. The role requires high-level expertise in power benchmarking, ASIC power analysis, and HW/SW development, with a...
- Synopsys, Inc. in Sunnyvale seeks an experienced ASIC digital design engineer with RTL ownership to deliver production RTL for LPDDR PHY IP across mobile and AI applications. You will optimize timing, power and area across multiple process nodes, develop Perl automation...
- ...Clara, CA, seeks a Senior Digital Design Engineer for its NVLink Fusion AI infrastructure SoC... ...analyze architectural requirements, implement RTL blocks, and collaborate with architects,... ...'s in EE/CE with 5+ years of relevant ASIC experience and experience with #J-18808-Ljbffr...
- Google in Sunnyvale, CA is seeking an experienced ASIC Design Engineer to develop custom silicon for data-center products, focusing on efficiency... .... You will define microarchitecture, write SystemVerilog RTL, and collaborate across software, architecture, and physical...
- ...startup in Sunnyvale is seeking an experienced RTL Design Tech Lead to drive micro-architecture and RTL development for complex ASIC/SoC programs. The role requires 10+ years... ...'s or Master's in Electrical/Computer Engineering. Competitive salary and comprehensive benefits...
$220k - $250k
...About the Role We're looking for a seasoned RTL Design Tech Lead to drive micro-... ...development, and technical execution for complex ASIC/SoC programs. This role combines deep... ...targets. Lead and mentor a team of RTL engineers (junior to senior ICs). Drive design reviews...Work from home- ...leading AI infrastructure startup is seeking an experienced ASIC Verification Engineer to develop verification strategies and ensure compliance... ...ASIC verification experience, particularly in data center networking. The candidate will collaborate on complex ASIC designs and...
- NVIDIA is looking for a Senior ASIC Design Engineer based in Santa Clara, California. You will be a key member of the GPU Design team, implementing high-performance, area-efficient RTL for leading SoCs and GPUs. The ideal candidate has a Bachelor's degree in Electrical...
$185k - $250k
A Silicon Valley-based hardware startup is looking for a highly experienced Post-Silicon ASIC Validation Engineer. The role involves leading validation of complex networking ASICs and chiplet-based architectures. The ideal candidate has strong expertise in post-silicon...- ...Apple’s Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer to join our dynamic group. In this role, you will develop custom... ...implementation, and verification of complex ASICs. Develop RTL using SystemVerilog and perform synthesis....
$138k - $197k
...specifications.Develop SystemVerilog RTL to implement logic for ASIC products according to established... ...qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, Computer... ...fabric bridges and sensor telemetry network, also participate in developing...Worldwide$2,000 per month
...magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs,... ...models and extremely deep chain-of-thought reasoning. RTL Design Engineer As an RTL Engineer at Etched, you will be critical in...Work experience placementWork at officeRelocation package$163k - $236k
...specification and interacting with design engineers to identify important verification... ...in verifying digital logic at RTL using SystemVerilog/UVM for ASICs.Preferred qualifications:Master's... ...AI for Google Cloud, Google Global Networking, Data Center operations, systems research...Worldwide- NVIDIA Corporation in Santa Clara, CA seeks a Senior ASIC Design Engineer for Clocks IP to architect clock domains for GPUs/CPUs, collaborating... ...requirements. Role involves implementing clocking topologies in RTL, evaluating trade-offs across DFx, physical implementation...
$186k - $407k
...communicate and advance faster than ever.Principal ASIC Design EngineerAbout the RoleAt Micron, we... ...to execute.As the Principal ASIC Design Engineer, you will be the primary digital... ...the authoritative digital voice — owning RTL design and micro-architecture of the digital...Full timeFor contractorsLocal areaImmediate start$168k - $310.5k
NVIDIA Gruppe in Santa Clara is seeking experienced ASIC Design Engineers to design and implement advanced SoCs and GPUs. The ideal candidate will have a Master's or PhD in Electrical Engineering or Computer Science, with over 8 years of related experience. This role involves...- GlobalFoundries in Santa Clara, CA is seeking a PMTS Digital Design Engineer to drive architecture implementation, microarchitecture development, and RTL design of high-performance processor cores and subsystems. You will partner with architecture, verification, physical...
$174k - $352.5k
## Principal ASIC Design EngineerApplylocations: Sunnyvale, California... ...used in high performance networking chips.* Write detailed functional... ...timing closure. Fix timing in RTL to meet the frequency target.*... ...to new college-grad/junior engineers and interns.**Recommended skills...Work experience placementWork at office2 days per week- ...Micron Technology is seeking a Principal ASIC Design Engineer to join its Interface Pathfinding team, which focuses on innovating memory and storage... ...-out. Responsibilities: Own the micro-architecture and RTL implementation of digital soft IP blocks in synthesizable...
$187k - $311.4k
Qualcomm is seeking a Wireless Design Engineer in Santa Clara, CA. You will define specifications, develop RTL, and collaborate with hardware, RF, and firmware teams. Ideal candidates have extensive experience in software/hardware engineering and solid expertise in RTL...$186.9k - $267.7k
...specification reviews.Implement Verilog RTL to meet timing and performance... ...methodology.Mentor junior engineers on performing project tasks... ...engineering and 8+ years of ASIC Design experience, or Master’s... .... Add to that our worldwide network of doers and experts, and you’...Full timeTemporary workLocal areaFlexible hours$167.7k - $245.2k
...organization, collaborating closely with Front-end RTL and backend physical design teams to... ...is essential to delivering advanced networking silicon aligned with Cisco Silicon One’s... ...'s Degree in Electrical or Computer Engineering required with at least 7 years of experiencePrior...Full timeTemporary workLocal areaFlexible hours
Do you want to receive more vacancies?
Subscribe and receive similar vacancies to RTL Engineer, Networking ASIC. Be the first to apply!



