RISC-V Power & Clock Design Engineer
Sifive
SiFive in Santa Clara, California, is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer. This role involves designing industry-leading CPU and interconnect IP, focusing on RISC-V architecture. The ideal candidate will have at least 3 years of experience in CPU and SoC designs and a strong understanding of power management techniques. Join us in transforming the future of compute! #J-18808-Ljbffr Sifive
Vacancy posted 2 days ago
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