Memory Subsystem Architect: DDR6/HBM & High-Speed PHY
Rambus.com
Rambus is seeking a Senior Principal Engineer in San Jose, CA, to lead memory subsystem architecture for next-generation DRAM solutions. You will drive DDR5/6, LPDDR5/6, and HBM architectures, collaborate with ASIC/PHY teams, and guide design verification and interoperability efforts. The role reports to the VP of Engineering within the Memory Interface Division, and Rambus emphasizes hybrid work with onsite emphasis and remote options. #J-18808-Ljbffr Rambus.com
Vacancy posted 3 days ago
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