Senior Physical Design Engineer - SoC/Sub-7nm Expert
eInfochips (An Arrow Company)
eInfochips, an Arrow company, seeks an experienced physical design engineer to drive synthesis, PnR, and timing convergence for ASIC partitions on-site in San Jose, CA. You will work with architects, RTL, and DFT teams to ensure design signoffs and address EM/IR challenges. Preferred candidates have 7+ years in SoC physical design, deep PD flows, and proficiency with Innovus and Genus. This role emphasizes tight schedules and collaboration with EDA vendors.
#J-18808-LjbffrVacancy posted 3 days ago
Similar jobs that could be interesting for youBased on the Senior Physical Design Engineer - SoC/Sub-7nm Expert in San Jose, CA vacancy
- ...Arrow in San Jose, California is seeking a senior ASIC physical design engineer to execute synthesis, PnR, and STA for assigned partitions of an SoC under strict schedules. You will collaborate with architects, RTL designers, and DFT teams to resolve issues, drive EM/IR...Senior
Uncrewed Engineering Jobs
San Jose, CA2 days ago - ...Tsavorite Scalable Intelligence, Inc. is seeking an experienced Physical Design Engineer to drive implementation and signoff of complex, multimillion-instance, high-speed SoC subsystems on sub-5nm nodes. You will own convergence end to end across synthesis, place and...Suggested
Tsavorite Scalable Intelligence, Inc.
Milpitas, CA3 days ago - ...Qualcomm Technologies, Inc. in Santa Clara, California is seeking a Physical Design Engineer to contribute across ASIC/SoC projects, including floorplanning, CTS, and low-power strategies. The role involves executing the full physical design flow, collaborating with cross...Senior
QUALCOMM, Inc.
Santa Clara, CA3 days ago - ...Qualcomm Technologies, Inc. in Santa Clara, CA is seeking talented Physical Design Engineers to join our growing SoC and ASIC Design organization. You will drive all stages of the physical design flow for high-performance ASICs/SoCs, including floorplanning, CTS, routing...Senior
- ...SK hynix memory solutions is seeking a Sr. Staff Physical Design Engineer to lead RTL-to-GDS implementation for advanced-node SoCs. You will guide synthesis, placement, CTS, and routing while collaborating with front-end, DFT, power, and analog teams to optimize PPA and...Senior
SKHMS Corporation
San Jose, CA3 days ago $136k - $218.5k
...intelligence.We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our dynamic and... ...-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or... ....Strong experience in full-chip/sub-chip Static Timing Analysis (STA),...SeniorFull timeShift workNvidia
Santa Clara, CA2 days ago$136k - $218.5k
....We are now looking for a motivated Senior Physical Design and Timing Engineer to join our dynamic and growing team... ...low-power NVIDIA CPUs, GPUs, LPUs and SoCs at block level, cluster level, and/... ....Hands-on experience in block, sub-chip, and full-chip level Static Timing...SeniorFull timeNvidia
Santa Clara, CA3 days ago- ...Baya Systems seeks a Principal Engineer-Physical Design for a fully remote role serving the US. The candidate will own RTL to GDS physical implementation... ...micro-architects to drive high-performance, power-efficient SoC designs is essential. Qualifications include a bachelor’s...Remote work
Baya Systems
Santa Clara, CA3 days ago - Position:Physical Design Engineer II (eInfochips Inc)Job Description:What You'll Be Doing:Execute synthesis, PNR, and STA... ...design techniques.Experience in System-on-Chip (SoC) design and implementation.Expertise in sub-7nm node technologies.Familiarity with industry-standard...Full timeWork at office
Arrow ECS
San Jose, CA1 day ago $213k - $287.5k
Annapurna Labs designs silicon and software that accelerates innovation... ...change the world.Custom SoCs (System on Chip) live at the... .... We’re looking for an ASIC Physical Design Engineer to help us trail-blaze new... .../subsystems (FC/Innovus)- Expert knowledge of industry-standard...Local areaFlexible hoursAmazon
Cupertino, CA22 hours ago$168k - $264.5k
...can make a lasting impact on the world.We are looking for a physical design engineer to be a part of NVIDIA’s physical design (PD) methodology team... ...for implementation of GPU, CPU, Network processors and SOC, with emphasis on PPA (Power, Performance, Area) and runtime...SeniorFull timeRemote workNvidia
Santa Clara, CA1 day ago$136k - $218.5k
NVIDIA is looking for a Senior SOC Design Engineer to join our SOC Design team! At NVIDIA, you'll collaborate with brilliant minds... ...technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software, DFT, and more...SeniorFull timeNvidia
Santa Clara, CA1 day ago$164.47k - $232.19k
...better brings. We work every single day to design and manufacture silicon products that... ...wonderful.The Role and Impact:As a GPU Physical Design Engineer, you will play a critical role in the... ...physical design challenges, including SoC integration and timing closure.Background...SeniorFull timeInternshipLocal areaImmediate startWorldwideShift workIntel
Santa Clara, CA4 days ago$138k - $206k
...global leader whose innovative designs are pushing the boundaries of what... ...both hardware and software engineers to identify and address the unique... ...policy.What You’ll DoOwn the physical implementation of memory-centric computing IP and SoC partitions from RTL netlist to...SeniorWork at officeFlexible hoursNight shiftSamsung Semiconductor
San Jose, CA22 hours ago- ...Apple Inc. in Cupertino, California, is seeking a Senior IC Design Engineer to lead power reduction and physical design for advanced node SoCs. You will perform static and dynamic power analysis, implement low power techniques, fix violations, and drive tape-out readiness...
Apple Inc.
Cupertino, CA1 day ago - ...NVIDIA Corporation is seeking a Senior ASIC Design Engineer in Santa Clara, CA to design and implement high‑performance GPU and SoC sub-systems. You will own micro-architecture, write RTL, and ensure fully verified, timing-clean designs while supporting post‑silicon validation...Senior
- ...Samsung Semiconductor is hiring a Principal Engineer, SOC Design to lead architectural and RTL development for next-gen memory-focused SoCs.... ...verification engineers to ensure robust designs. You will work with physical design on timing, synthesis, DFT, and STA, shaping product...Senior
- ...Efficient Computer seeks a Senior Design Engineer to design, integrate, and sign off RTL for blocks across our power-efficient SoC, focusing on on-chip interconnect and memory interfaces... ...will collaborate with architects, DV, physical design, and firmware to tape out a...SeniorNight shift
Efficient Computer
San Jose, CA3 days ago - ...Semiconductor's DRAM Development Lab in San Jose seeks a Principal Engineer for SOC design to advance memory/storage silicon solutions. You will drive... ...-level integration, and coordinate with verification and physical-design teams to ensure a robust SoC. The role demands...Senior
$200k - $300k
...Role Overview We are looking for talented Design Verification Engineers to help verify and deliver Velaura’s next-generation Physical AI SoC. In this role, you will work closely witharchitects, RTL engineers, software engineers, and system teams to verify complexhardware...SeniorFlexible hoursVelaura AI, Inc.
Santa Clara, CA3 days ago- ...Astera Labs seeks a Principal Digital Design Engineer to lead front-end circuit design for high-performance network controllers, including... ..., and block-level verification. You will bring 8+ years in SoC/silicon for Switch ASIC, Networking, Server or Storage, with strong...
$100k
...contributors of all seniorities.We’re looking for a Timing Engineer to join our silicon... ..., high-performance designs. You’ll collaborate... ...logic, DFT, and physical design teams to debug... ...RISC-V CPUs and AI SoCs.Advanced STA methodologies... ...tailored to modern sub-micron process...Permanent employmentTenstorrent
Santa Clara, CA1 day ago$136k - $218.5k
...looking for a top-notch ASIC engineer to join the team. The... ...with the front design team to understand the... ...team to help craft the physical floorplan of the chip.... ...information to GPU, CPU and SOC verification team, timing... ....Understanding of sub-micron silicon issues like...SeniorFull timeWork experience placementNvidia
Santa Clara, CA1 day ago$136k - $218.5k
As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network and last... ....What we need to see:Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or...SeniorFull timeNvidia
Santa Clara, CA3 days ago- ...future. Whether you’re designing next-gen processors, enabling... ...-signal layout design engineer with supervisory role... ....Block level physical implementation which includes... ...in lower process nodes (7nm or below)Good understanding... ...flow or digital SOC flow is a benefitExperience...SeniorWork experience placementRemote work
AMD
San Jose, CA3 days ago - ...the future. Whether you’re designing next-gen processors,... ...contribute to advanced-node physical design for complex ASIC and SoC products, driving implementation... ...technology, and product engineering teams, you will help... ...hands-on physical design expert with a strong track...Senior
AMD
Santa Clara, CA1 day ago - ...Velaura AI, Inc. is seeking a Design Verification Engineer to verify a next-generation Physical AI SoC. You will collaborate with architects, RTL and software teams to ensure correctness, performance, and safety across RTL blocks and full HW/SW systems under real workloads...Senior
Velaura AI, Inc.
Santa Clara, CA3 days ago - ...Ayar Labs is seeking an ASIC Sr. Staff Engineer to lead design, bring-up and debug of complex digital subsystems in an electro-optical SoC. You will work in a small IC design team, hands-on and independent, delivering clear specifications and robust RTL. You will collaborate...Senior
Ayar Labs, Inc.
San Jose, CA3 days ago - ...TetraMem in San Jose, CA is seeking a senior RTL design engineer to lead RTL design, simulation, and verification for ASIC/SoC products, ensuring robust and efficient designs. You will integrate IP blocks, perform PPA analysis, collaborate with backend, and drive tapeout...Senior
TetraMem - Accelerate The World
San Jose, CA2 days ago $100k
...our team and looking for contributors of all seniorities.Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable... ..., with solid understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design challenges....Permanent employmentTenstorrent
Santa Clara, CA22 hours ago
Do you want to receive more vacancies?
Subscribe and receive similar vacancies to Senior Physical Design Engineer - SoC/Sub-7nm Expert. Be the first to apply!
Related searches
- staff design engineer San Jose, CA
- product engineer San Jose, CA
- senior manager product engineering San Jose, CA
- new product engineer San Jose, CA
- chief design engineer San Jose, CA
- senior fpga design engineer San Jose, CA
- senior software design engineer San Jose, CA
- cad design engineer solidworks San Jose, CA
- sr. product engineer San Jose, CA
- digital design engineer San Jose, CA