Design Verification Engineer
$190k - $250kAyar Labs
Ayar Labs in San Jose, CA is seeking a Principal Engineer, Digital Verification and Emulation to spearhead verification efforts for our silicon photonic chips. The ideal candidate has over 12 years of experience in ASIC/SoC verification and expertise with hardware emulation platforms.
This role involves collaborating closely with various teams while leading the verification methodology and ensuring readiness for simulation and tape-out. A competitive salary of $190,000 - $250,000 is offered for this on-site role.
#J-18808-LjbffrVacancy posted 4 days ago
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