Senior RTL Verification Engineer — SystemVerilog & UVM
$160k - $220kDelos Data
Delos Data, located in Palo Alto, California, is seeking a Senior RTL Verification Engineer to ensure the functionality and quality of complex digital designs across ASIC and FPGA platforms. This role involves building robust verification environments and collaborating with RTL design engineers. The ideal candidate will have 7+ years of experience, strong hands-on skills in UVM and SystemVerilog, and will thrive in a dynamic startup environment. Compensation includes a target salary of $160,000 – $220,000 per year plus equity and benefits. #J-18808-Ljbffr Delos Data
Vacancy posted 2 days ago
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